CRICRATE : A cricket match conduction and player evaluation framework
- Authors: Uddin, Md Ashraf , Hasan, Mahmudul , Halder, Sajal , Ahamed, Sajeeb , Acharjee, Uzzal
- Date: 2019
- Type: Text , Conference paper
- Relation: International Conference on Emerging Technologies in Data Mining and Information Security, IEMIS 2018 Vol. 755, p. 491-500
- Full Text: false
- Reviewed:
- Description: Cricket has appeared as one of the most favorite outdoor games in the present world. The cricket players represent a country and create economic, political, and diplomatic relations among nations. The cricket board of a country requires selecting the fittest players for the upcoming team among some good players. We propose an architecture called Cricket Match Conduction and Player Evaluation Framework by developing some algorithms to predict the score of the players as well as the algorithm to evaluate the man of the match in one day or test cricket match. We implemented the framework by Weka and web technology. © Springer Nature Singapore Pte Ltd. 2019.
An improved pipelined processor architecture eliminating branch and jump penalty
- Authors: Hasan, Raquibal , Rahman, M. S. , Hasan, Masud , Hasan, Mahmudul , Ali, Mortuza
- Date: 2010
- Type: Text , Conference proceedings
- Relation: Computer Engineering and Applications (ICCEA), Bali, ICCEA 2010, 19th March 2010; published in 2010 2nd International Conference on Computer Engineering and Applications, ICCEA 2010 Vol. 1, p. 621-625
- Full Text: false
- Reviewed:
- Description: Control dependencies are one of the major limitations to increase the performance of pipelined processors. This paper deals with eliminating penalties in pipelined processor. We present our discussion in the light of MIPS pipelined processor architecture. Here we present an improved pipelined processor architecture eliminating branch and jump penalty. In the proposed architecture CPI for branch and jump instruction is less than that of MIPS architecture. We also have shown the design of the required cache memory cell for the improved architecture.
- Description: Second International Conference on Computer Engineering and Applications (ICCEA), 2010