Dual cost function model predictive direct speed control with duty ratio optimization for PMSM drives
- Liu, Ming, Hu, Jiefeng, Chan, Ka, Or, Siu, Ho, Siu, Xu, Wenzheng, Zhang, Xian
- Authors: Liu, Ming , Hu, Jiefeng , Chan, Ka , Or, Siu , Ho, Siu , Xu, Wenzheng , Zhang, Xian
- Date: 2020
- Type: Text , Journal article
- Relation: IEEE Access Vol. 8, no. (2020), p. 126637-126647
- Full Text:
- Reviewed:
- Description: Traditional speed control of permanent magnet synchronous motors (PMSMs) includes a cascaded speed loop with proportional-integral (PI) regulators. The output of this outer speed loop, i.e. electromagnetic torque reference, is in turn fed to either the inner current controller or the direct torque controller. This cascaded control structure leads to relatively slow dynamic response, and more importantly, larger speed ripples. This paper presents a new dual cost function model predictive direct speed control (DCF-MPDSC) with duty ratio optimization for PMSM drives. By employing accurate system status prediction, optimized duty ratios between one zero voltage vector and one active voltage vector are firstly deduced based on the deadbeat criterion. Then, two separate cost functions are formulated sequentially to refine the combinations of voltage vectors, which provide two-degree-of-freedom control capability. Specifically, the first cost function results in better dynamic response, while the second one contributes to speed ripple reduction and steady-state offset elimination. The proposed control strategy has been validated by both Simulink simulation and hardware-in-the-loop (HIL) experiment. Compared to existing control methods, the proposed DCF-MPDSC can reach the speed reference rapidly with very small speed ripple and offset. © 2013 IEEE.
- Description: This work was supported in part by the Research Grants Council of the Hong Kong Special Administrative Region (HKSAR) Government under Grant R5020-18, and in part by the Innovation and Technology Commission of the HKSAR Government to the Hong Kong Branch of National Rail Transit Electrification and Automation Engineering Technology Research Center under Grant K-BBY1.
- Authors: Liu, Ming , Hu, Jiefeng , Chan, Ka , Or, Siu , Ho, Siu , Xu, Wenzheng , Zhang, Xian
- Date: 2020
- Type: Text , Journal article
- Relation: IEEE Access Vol. 8, no. (2020), p. 126637-126647
- Full Text:
- Reviewed:
- Description: Traditional speed control of permanent magnet synchronous motors (PMSMs) includes a cascaded speed loop with proportional-integral (PI) regulators. The output of this outer speed loop, i.e. electromagnetic torque reference, is in turn fed to either the inner current controller or the direct torque controller. This cascaded control structure leads to relatively slow dynamic response, and more importantly, larger speed ripples. This paper presents a new dual cost function model predictive direct speed control (DCF-MPDSC) with duty ratio optimization for PMSM drives. By employing accurate system status prediction, optimized duty ratios between one zero voltage vector and one active voltage vector are firstly deduced based on the deadbeat criterion. Then, two separate cost functions are formulated sequentially to refine the combinations of voltage vectors, which provide two-degree-of-freedom control capability. Specifically, the first cost function results in better dynamic response, while the second one contributes to speed ripple reduction and steady-state offset elimination. The proposed control strategy has been validated by both Simulink simulation and hardware-in-the-loop (HIL) experiment. Compared to existing control methods, the proposed DCF-MPDSC can reach the speed reference rapidly with very small speed ripple and offset. © 2013 IEEE.
- Description: This work was supported in part by the Research Grants Council of the Hong Kong Special Administrative Region (HKSAR) Government under Grant R5020-18, and in part by the Innovation and Technology Commission of the HKSAR Government to the Hong Kong Branch of National Rail Transit Electrification and Automation Engineering Technology Research Center under Grant K-BBY1.
A new hybrid cascaded switched-capacitor reduced switch multilevel inverter for renewable sources and domestic loads
- Rezaei, Mohammad, Nayeripour, Majid, Hu, Jiefeng, Band, Shahab, Mosavi, Amir, Khooban, Mohammad-Hassan
- Authors: Rezaei, Mohammad , Nayeripour, Majid , Hu, Jiefeng , Band, Shahab , Mosavi, Amir , Khooban, Mohammad-Hassan
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Access Vol. 10, no. (2022), p. 14157-14183
- Full Text:
- Reviewed:
- Description: This multilevel inverter type summarizes an output voltage of medium voltage based on a series connection of power cells employing standard configurations of low-voltage components. The main problems of cascaded switched-capacitor multilevel inverters (CSCMLIs) are the harmful reverse flowing current of inductive loads, the large number of switches, and the surge current of the capacitors. As the number of switches increases, the reliability of the inverter decreases. To address these issues, a new CSCMLI is proposed using two modules containing asymmetric DC sources to generate 13 levels. The main novelty of the proposed configuration is the reduction of the number of switches while increasing the maximum output voltage. Despite the many similarities, the presented topology differs from similar topologies. Compared to similar structures, the direction of some switches is reversed, leading to a change in the direction of current flow. By incorporating the lowest number of semiconductors, it was demonstrated that the proposed inverter has the lowest cost function among similar inverters. The role of switched-capacitor inrush current in the selection of switch, diode, and DC source for inverter operation in medium and high voltage applications is presented. The inverter performance to supply the inductive loads is clarified. Comparison of the simulation and experimental results validates the effectiveness of the proposed inverter topology, showing promising potentials in photovoltaic, buildings, and domestic applications. A video demonstrating the experimental test, and all manufacturing data are attached. © 2013 IEEE.
- Authors: Rezaei, Mohammad , Nayeripour, Majid , Hu, Jiefeng , Band, Shahab , Mosavi, Amir , Khooban, Mohammad-Hassan
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Access Vol. 10, no. (2022), p. 14157-14183
- Full Text:
- Reviewed:
- Description: This multilevel inverter type summarizes an output voltage of medium voltage based on a series connection of power cells employing standard configurations of low-voltage components. The main problems of cascaded switched-capacitor multilevel inverters (CSCMLIs) are the harmful reverse flowing current of inductive loads, the large number of switches, and the surge current of the capacitors. As the number of switches increases, the reliability of the inverter decreases. To address these issues, a new CSCMLI is proposed using two modules containing asymmetric DC sources to generate 13 levels. The main novelty of the proposed configuration is the reduction of the number of switches while increasing the maximum output voltage. Despite the many similarities, the presented topology differs from similar topologies. Compared to similar structures, the direction of some switches is reversed, leading to a change in the direction of current flow. By incorporating the lowest number of semiconductors, it was demonstrated that the proposed inverter has the lowest cost function among similar inverters. The role of switched-capacitor inrush current in the selection of switch, diode, and DC source for inverter operation in medium and high voltage applications is presented. The inverter performance to supply the inductive loads is clarified. Comparison of the simulation and experimental results validates the effectiveness of the proposed inverter topology, showing promising potentials in photovoltaic, buildings, and domestic applications. A video demonstrating the experimental test, and all manufacturing data are attached. © 2013 IEEE.
An adaptive fault ride-through scheme for grid-forming inverters under asymmetrical grid faults
- Li, Zilin, Chan, Ka, Hu, Jiefeng, Or, Siu
- Authors: Li, Zilin , Chan, Ka , Hu, Jiefeng , Or, Siu
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Transactions on Industrial Electronics Vol. 69, no. 12 (2022), p. 12912-12923
- Full Text:
- Reviewed:
- Description: Three-phase four-wire grid-forming (GFM) inverters are promising to interface distributed energy resources into low-voltage networks. However, these inverters are prone to overcurrent under grid faults. Physically increasing the inverter current capacity is not cost-effective to cope with complicated fault conditions. In this article, an adaptive fault ride-through (FRT) scheme based on instantaneous saturators and virtual negative- and zero-sequence resistances is proposed. It features not only overcurrent limitation by modifying voltage references, but also seamless transition between normal and grid fault conditions. The proposed FRT scheme is first analyzed from different aspects, including the virtual sequence resistances, grid short-circuit ratio, fault types, and fault levels. The virtual sequence resistances are then designed to be adaptive to ensure high voltage quality at the healthy phase. The proposed FRT scheme is verified by MATLAB/Simulink simulations under asymmetrical faults. A laboratory platform with a grid-connected 3kW GFM inverter is further constructed to demonstrate its effectiveness (a video of the experimental results under three asymmetrical faults is attached). © 1982-2012 IEEE.
- Authors: Li, Zilin , Chan, Ka , Hu, Jiefeng , Or, Siu
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Transactions on Industrial Electronics Vol. 69, no. 12 (2022), p. 12912-12923
- Full Text:
- Reviewed:
- Description: Three-phase four-wire grid-forming (GFM) inverters are promising to interface distributed energy resources into low-voltage networks. However, these inverters are prone to overcurrent under grid faults. Physically increasing the inverter current capacity is not cost-effective to cope with complicated fault conditions. In this article, an adaptive fault ride-through (FRT) scheme based on instantaneous saturators and virtual negative- and zero-sequence resistances is proposed. It features not only overcurrent limitation by modifying voltage references, but also seamless transition between normal and grid fault conditions. The proposed FRT scheme is first analyzed from different aspects, including the virtual sequence resistances, grid short-circuit ratio, fault types, and fault levels. The virtual sequence resistances are then designed to be adaptive to ensure high voltage quality at the healthy phase. The proposed FRT scheme is verified by MATLAB/Simulink simulations under asymmetrical faults. A laboratory platform with a grid-connected 3kW GFM inverter is further constructed to demonstrate its effectiveness (a video of the experimental results under three asymmetrical faults is attached). © 1982-2012 IEEE.
A fault-tolerant cascaded switched-capacitor multilevel inverter for domestic applications in smart grids
- Akbari, Ehsan, Teimouri, Ali, Saki, Mojtaba, Rezaei, Mohammad, Hu, Jiefeng, Band, Shahab, Pai, Hao-Ting, Mosavi, Amir
- Authors: Akbari, Ehsan , Teimouri, Ali , Saki, Mojtaba , Rezaei, Mohammad , Hu, Jiefeng , Band, Shahab , Pai, Hao-Ting , Mosavi, Amir
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Access Vol. 10, no. (2022), p. 110590-110602
- Full Text:
- Reviewed:
- Description: Cascaded multilevel inverters (MLIs) generate an output voltage using series-connected power modules that employ standard configurations of low-voltage components. Each module may employ one or more switched capacitors to double or quadruple its input voltage. The higher number of switched capacitors and semiconductor switches in MLIs compared to conventional two-level inverters has led to concerns about overall system reliability. A fault-tolerant design can mitigate this reliability issue. If one part of the system fails, the MLI can continue its planned operation at a reduced level rather than the entire system failing, which makes the fault tolerance of the MLI particularly important. In this paper, a novel fault location technique is presented that leads to a significant reduction in fault location detection time based on the reliability priority of the components of the proposed fault-tolerant switched capacitor cascaded MLI (CSCMLI). The main contribution of this paper is to reduce the number of MLI switches under fault conditions while operating at lower levels. The fault-tolerant inverter requires fewer switches at higher reliability, and the comparison with similar MLIs shows a faster dynamic response of fault detection and reduced fault location detection time. The experimental results confirm the effectiveness of the presented methods applied in the CSCMLI. Also, all experimental data including processor code, schematic, PCB, and video of CSCMLI operation are attached. © 2013 IEEE.
- Authors: Akbari, Ehsan , Teimouri, Ali , Saki, Mojtaba , Rezaei, Mohammad , Hu, Jiefeng , Band, Shahab , Pai, Hao-Ting , Mosavi, Amir
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Access Vol. 10, no. (2022), p. 110590-110602
- Full Text:
- Reviewed:
- Description: Cascaded multilevel inverters (MLIs) generate an output voltage using series-connected power modules that employ standard configurations of low-voltage components. Each module may employ one or more switched capacitors to double or quadruple its input voltage. The higher number of switched capacitors and semiconductor switches in MLIs compared to conventional two-level inverters has led to concerns about overall system reliability. A fault-tolerant design can mitigate this reliability issue. If one part of the system fails, the MLI can continue its planned operation at a reduced level rather than the entire system failing, which makes the fault tolerance of the MLI particularly important. In this paper, a novel fault location technique is presented that leads to a significant reduction in fault location detection time based on the reliability priority of the components of the proposed fault-tolerant switched capacitor cascaded MLI (CSCMLI). The main contribution of this paper is to reduce the number of MLI switches under fault conditions while operating at lower levels. The fault-tolerant inverter requires fewer switches at higher reliability, and the comparison with similar MLIs shows a faster dynamic response of fault detection and reduced fault location detection time. The experimental results confirm the effectiveness of the presented methods applied in the CSCMLI. Also, all experimental data including processor code, schematic, PCB, and video of CSCMLI operation are attached. © 2013 IEEE.
Adaptation of a real-time deep learning approach with an analog fault detection technique for reliability forecasting of capacitor banks used in mobile vehicles
- Rezaei, Mohammad, Fathollahi, Arman, Rezaei, Sajad, Hu, Jiefeng, Gheisarnejad, Meysam, Teimouri, Ali, Rituraj, Rituraj, Mosavi, Amir, Khooban, Mohammad-Hassan
- Authors: Rezaei, Mohammad , Fathollahi, Arman , Rezaei, Sajad , Hu, Jiefeng , Gheisarnejad, Meysam , Teimouri, Ali , Rituraj, Rituraj , Mosavi, Amir , Khooban, Mohammad-Hassan
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Access Vol. 10, no. (2022), p. 132271-132287
- Full Text:
- Reviewed:
- Description: The DC-Link capacitor is defined as the essential electronics element which sources or sinks the respective currents. The reliability of DC-link capacitor-banks (CBs) encounters many challenges due to their usage in electric vehicles. Heavy shocks may damage the internal capacitors without shutting down the CB. The fundamental development obstacles of CBs are: lack of considering capacitor degradation in reliability assessment, the impact of unforeseen sudden internal capacitor faults in forecasting CB lifetime, and the faults consequence on CB degradation. The sudden faults change the CB capacitance, which leads to reliability change. To more accurately estimate the reliability, the type of the fault needs to be detected for predicting the correct post-fault capacitance. To address these practical problems, a new CB model and reliability assessment formula covering all fault types are first presented, then, a new analog fault-detection method is presented, and a combination of online-learning long short-term memory (LSTM) and fault-detection method is subsequently performed, which adapt the sudden internal CB faults with the LSTM to correctly predict the CB degradation. To confirm the correct LSTM operation, four capacitors degradation is practically recorded for 2000-hours, and the off-line faultless degradation values predicted by the LSTM are compared with the actual data. The experimental findings validate the applicability of the proposed method. The codes and data are provided. © 2013 IEEE.
- Authors: Rezaei, Mohammad , Fathollahi, Arman , Rezaei, Sajad , Hu, Jiefeng , Gheisarnejad, Meysam , Teimouri, Ali , Rituraj, Rituraj , Mosavi, Amir , Khooban, Mohammad-Hassan
- Date: 2022
- Type: Text , Journal article
- Relation: IEEE Access Vol. 10, no. (2022), p. 132271-132287
- Full Text:
- Reviewed:
- Description: The DC-Link capacitor is defined as the essential electronics element which sources or sinks the respective currents. The reliability of DC-link capacitor-banks (CBs) encounters many challenges due to their usage in electric vehicles. Heavy shocks may damage the internal capacitors without shutting down the CB. The fundamental development obstacles of CBs are: lack of considering capacitor degradation in reliability assessment, the impact of unforeseen sudden internal capacitor faults in forecasting CB lifetime, and the faults consequence on CB degradation. The sudden faults change the CB capacitance, which leads to reliability change. To more accurately estimate the reliability, the type of the fault needs to be detected for predicting the correct post-fault capacitance. To address these practical problems, a new CB model and reliability assessment formula covering all fault types are first presented, then, a new analog fault-detection method is presented, and a combination of online-learning long short-term memory (LSTM) and fault-detection method is subsequently performed, which adapt the sudden internal CB faults with the LSTM to correctly predict the CB degradation. To confirm the correct LSTM operation, four capacitors degradation is practically recorded for 2000-hours, and the off-line faultless degradation values predicted by the LSTM are compared with the actual data. The experimental findings validate the applicability of the proposed method. The codes and data are provided. © 2013 IEEE.
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