Control dependencies are one of the major limitations to increase the performance of pipelined processors. This paper deals with eliminating penalties in pipelined processor. We present our discussion in the light of MIPS pipelined processor architecture. Here we present an improved pipelined processor architecture eliminating branch and jump penalty. In the proposed architecture CPI for branch and jump instruction is less than that of MIPS architecture. We also have shown the design of the required cache memory cell for the improved architecture.
Second International Conference on Computer Engineering and Applications (ICCEA), 2010