Minimization of CTS of k-CNOT circuits for SSF and MSF model
- Authors: Ibrahim, Yousef , Chowdhury, Ahsan , Babu, Hafiz
- Date: 2008
- Type: Text , Conference proceedings
- Relation: 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008; Boston, MA; United States; 1st -3rd October 2008; published in proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems pg. 290-298 p. 290-298
- Full Text: false
- Reviewed:
- Description: In this paper, we consider the problem of testing reversible circuits for a particular fault model: Stuck-at Fault Model. We propose a design-for-test construction technique for k-CNOT circuit having k ≥ 1 and only 2 test vector (i.e. minimal) suffice as their complete test set. We have also shown the way to exploit our method for the case of 0-CNOT circuits. Finally we provide some experimental results for the proposed method and compare it with existing method to show how the proposed one outperforms the existing one both in terms of number of test vectors of complete test set and number of gates need to be replaced in the design-for-test. © 2008 IEEE.
- Description: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
On the minimization of complete test set of reversible k-CNOT circuits for Stuck-at Fault model
- Authors: Ibrahim, Yousef , Chowdhury, Ahsan , Babu, Hafiz
- Date: 2008
- Type: Text , Conference paper
- Relation: Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference
- Full Text: false
- Reviewed:
- Description: In this paper, we propose an algorithm that produces the complete test set (CTS) of a reversible circuit for Single stuck-at fault (SSF) and multiple-stuck-at fault (MSF) models. Our algorithm works only for an important subclass of reversible circuits - the circuits consisting of k-CNOT gates (k ges 2) though, any n-wire circuit having 0-CNOT or 1-CNOT gates can be converted to a (n + 2) wire circuit having only k-CNOT gates with k ges 2 with some additional hardware cost. Generated complete test set is not necessarily optimal, but minimizing the size of the complete test set is our key concern. Finally we provide some experimental results for the proposed method and compare it with existing methods to show how it outperforms almost all of the existing algorithms in terms of number of elements of CTS but is outperformed by some of the existing ones in terms of hardware cost.