An improved pipelined processor architecture eliminating branch and jump penalty

Title: An improved pipelined processor architecture eliminating branch and jump penalty
Creator: Hasan, Raquibal; Rahman, M. S.; Hasan, Masud; Hasan, Mahmudul; Ali, Mortuza
Date: 2010
Type: Text; Conference proceedings
Identifier: http://researchonline.federation.edu.au/vital/access/HandleResolver/1959.17/103073
Identifier: vital:10863
Identifier: https://doi.org/10.1109/ICCEA.2010.126
Identifier: ISBN: 978-076953982-9
Abstract: Control dependencies are one of the major limitations to increase the performance of pipelined processors. This paper deals with eliminating penalties in pipelined processor. We present our discussion in the light of MIPS pipelined processor architecture. Here we present an improved pipelined processor architecture eliminating branch and jump penalty. In the proposed architecture CPI for branch and jump instruction is less than that of MIPS architecture. We also have shown the design of the required cache memory cell for the improved architecture.; Second International Conference on Computer Engineering and Applications (ICCEA), 2010
Relation: Computer Engineering and Applications (ICCEA), Bali, ICCEA 2010, 19th March 2010; published in 2010 2nd International Conference on Computer Engineering and Applications, ICCEA 2010 Vol. 1, p. 621-625
Rights: Copyright IEEE
Rights: This metadata is freely available under a CCO license
Subject: Reconfigurable architectures; Cache storage; Microprocessor chips
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