- Title
- On the minimization of complete test set of reversible k-CNOT circuits for Stuck-at Fault model
- Creator
- Ibrahim, Yousef; Chowdhury, Ahsan; Babu, Hafiz
- Date
- 2008
- Type
- Text; Conference paper
- Identifier
- http://researchonline.federation.edu.au/vital/access/HandleResolver/1959.17/75851
- Identifier
- vital:7446
- Identifier
-
https://doi.org/10.1109/ICCITECHN.2008.4803009
- Identifier
- ISBN:978-1-4244-2135-0
- Abstract
- In this paper, we propose an algorithm that produces the complete test set (CTS) of a reversible circuit for Single stuck-at fault (SSF) and multiple-stuck-at fault (MSF) models. Our algorithm works only for an important subclass of reversible circuits - the circuits consisting of k-CNOT gates (k ges 2) though, any n-wire circuit having 0-CNOT or 1-CNOT gates can be converted to a (n + 2) wire circuit having only k-CNOT gates with k ges 2 with some additional hardware cost. Generated complete test set is not necessarily optimal, but minimizing the size of the complete test set is our key concern. Finally we provide some experimental results for the proposed method and compare it with existing methods to show how it outperforms almost all of the existing algorithms in terms of number of elements of CTS but is outperformed by some of the existing ones in terms of hardware cost.
- Relation
- Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference
- Rights
- This metadata is freely available under a CCO license
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