- Title
- Minimization of CTS of k-CNOT circuits for SSF and MSF model
- Creator
- Ibrahim, Yousef; Chowdhury, Ahsan; Babu, Hafiz
- Date
- 2008
- Type
- Text; Conference proceedings
- Identifier
- http://researchonline.federation.edu.au/vital/access/HandleResolver/1959.17/103128
- Identifier
- vital:10866
- Identifier
-
https://doi.org/10.1109/DFT.2008.38
- Identifier
- ISBN:15505774
- Abstract
- In this paper, we consider the problem of testing reversible circuits for a particular fault model: Stuck-at Fault Model. We propose a design-for-test construction technique for k-CNOT circuit having k ≥ 1 and only 2 test vector (i.e. minimal) suffice as their complete test set. We have also shown the way to exploit our method for the case of 0-CNOT circuits. Finally we provide some experimental results for the proposed method and compare it with existing method to show how the proposed one outperforms the existing one both in terms of number of test vectors of complete test set and number of gates need to be replaced in the design-for-test. © 2008 IEEE.; Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
- Relation
- 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008; Boston, MA; United States; 1st -3rd October 2008; published in proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems pg. 290-298 p. 290-298
- Rights
- Copyright IEEE
- Rights
- This metadata is freely available under a CCO license
- Subject
- Construction technique; Design for test; Existing method; Fault model; MSF model; Number of gates; Reversible circuits; Stuck-at fault models; Test sets; Test vectors
- Reviewed
- Hits: 1517
- Visitors: 1507
- Downloads: 0
| Thumbnail | File | Description | Size | Format |
|---|